A manufacturing process for a semiconductor wafer includes the following steps: a slicing step of slicing thin plates (wafers) from a single crystal ingot, and other steps such as chamfering a wafer, lapping, etching, polishing, and cleaning.
A chemical etched wafer surface is processed in a mirror polishing into a mirror-surface having smoothness without strain. Mirror polishing of a silicon wafer is conducted while giving a prescribed load and a relative speed between the wafer and the polishing cloth, and supplying a polishing agent. As the polishing agent there is mainly used one prepared by dispersing colloidal silica or the like into an alkaline solution.
There is generally adopted as the polishing step a multistage polishing step of two or more stages including a coarse polishing stage (generally called a stock polishing stage) with the purpose of flattening, a final polishing stage with the purposes of improvement in surface roughness and elimination of polishing scratches and other type polishing.
In the stock polishing stage, there are used a hard polishing cloth (a velour type) obtained by impregnating a foamed urethane sheet, a non-woven fabric such as polyester or the like with urethane resin, and a high-performance polishing agent added with a polishing accelerator.
In the final polishing stage, there are used a suede like polishing cloth (a suede type) of two layers obtained by foaming urethane resin on a base cloth of a non-woven fabric, a polishing agent added with additives for control of cloudiness on a wafer surface called haze observed under a collimated light, and other requirements.
Especially, detailed description will be given of a suede type polishing cloth used in the final polishing stage. As shown in FIG. 1, the polishing cloth is formed such that a base material of polyester felt impregnated with polyurethane is coated (laminated) with polyurethane and a foamed layer is grown in the polyurethane, followed by removal of a surface section thereof to form the foamed layer with pores. This layer is called a nap layer. There is provided a sort of standard on a thickness or a length of the nap layer, whereas it is generally used over a range of a value on the order of 450 μm.
There have been occasionally generated on a surface of a final polished wafer micro-scratches and blind scratches that are considered to be caused by polishing. By generation of such scratches, there arises a problem that product yield decreases in a device fabrication process and other processes.
Herein, a micro-scratch (may be referred to as a polishing slight scratch) on a wafer surface is a very small polishing scratch to be counted at 0.10 μm or less in particle diameter with a particle counter.
Further, a blind scratch on a wafer surface is a defect (damage) that cannot be observed in ordinary appearance inspection and evaluated with a method wherein a wafer is subjected to preferential etching, followed by observation.